module cmd_enc(
         input          clk       ,
		 input          rst_n     ,
		 output [7:0]   data      ,
		 output         data_valid,
		 input          cmd_valid ,
		 input [15:0]   cmd_index ,//指令
		 input [31:0]   par_index  //参数

);
reg        data_valid_r;
reg [7:0]  data_r      ;
reg [15:0] cmd_index_r ;
reg [31:0] par_index_r ;
reg [7:0]  byte_cnt    ;
assign data       = data_r      ;
assign data_valid = data_valid_r;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
    cmd_index_r  <= 16'd0; 
    par_index_r  <= 32'd0;
    byte_cnt     <= 8'd0 ;
    data_r       <= 8'd0 ;
    data_valid_r <= 1'b0 ;
end
else 
begin
    if(cmd_valid) begin
        cmd_index_r <= cmd_index;
        par_index_r <= par_index;
        byte_cnt    <= 8'd8;
    end else begin
        cmd_index_r <= cmd_index_r;
        par_index_r <= par_index_r;
        byte_cnt    <= byte_cnt-(|byte_cnt);
    end
    data_valid_r <= |byte_cnt;
    if(byte_cnt == 8'd8)
        data_r <= 8'h44;
    else if(byte_cnt == 8'd7)
        data_r <= cmd_index_r[15:8];
    else if(byte_cnt == 8'd6)
        data_r <= cmd_index_r[7:0];
    else if(byte_cnt == 8'd5)
        data_r <= par_index_r[31:24];
    else if(byte_cnt == 8'd4)
        data_r <= par_index_r[23:16];
    else if(byte_cnt == 8'd3)
        data_r <= par_index_r[15:8];
    else if(byte_cnt == 8'd2)
        data_r <= par_index_r[7:0];
    else if(byte_cnt == 8'd1)
        data_r <= 8'd0;
    else
        data_r <= 8'd0;
end
end
endmodule 